Programmable logic arrays, conventionally known as PALs, a trademark of Monolithic Memories, Inc., are a family of logic devices known in the art for implementing combinatorial logic functions. A PAL in general has a programmable AND matrix and a nonprogrammable OR matrix, or vice versa, such that the programmer has a fairly limited flexibility in the logic functions which may be implemented.
More recently, a field programmable logic sequencer (FPLS) has been developed that includes an AND subarray and an OR subarray. The FPLS has a plurality of state registers connected to outputs of the OR subarray, the outputs of the state registers being fed back into the network as inputs of the product subarray. The FPLS thus can store a state for use in further combinatorial logic functions, and, through the programming of many combinatorial sequence product terms in the AND subarray, can be used to generate a plurality of different clock cycles on the outputs of the FPLS.
Using conventional FPLS's, timing sequences are constructed such that a separate programmable product term defines outputs for every triggering transition of an input clock pulse. This requires a wasteful number of programmable product terms that could be used for other purposes. If an external counter is used to reference the produced clock sequences, a number of external inputs and outputs of the FPLS must be dedicated.
A need has thus arisen in the industry for a more efficient way to produce timing sequences from a logic matrix, as well as for a versatile single logic chip that can be used for both state machine and waveform generating applications.